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november 2013 docid8827 rev 3 1/30 AN1517 application note designing with the steval-isa0 89v1 high efficiency dc-dc converter by massimili ano merisio introduction the l5972d device is a step-down monolithic power switching regulator capable of delivering up to 2 a at output voltages from 1.235 v to 35 v. the operating input voltage ranges from 4.4 v to 36 v. the device has been designed using bcdv technology and the power switching element is implemented throug h a p-channel dmos transistor. it does not require a bootstrap capacitor, and the duty cycle can range up to 100%. an internal oscillator fixes the switching fr equency at 250 khz. this mi nimizes the lc output filter. pulse-by-pulse and frequency foldback overcu rrent protection offe r effective protection against short-circuit. other features are volt age feed-forward, protection against feedback disconnection, and thermal shutdown. the devic e is housed in a thermally improved so-8 package (with 4 pins connected to gnd so that the thermal resistance junction to ambient is reduced to approximately one-half compared with a standard so-8 package. figure 1. demonstration board steval-isa089v1 (so-8) board dimensions: 34 x 43 mm figure 2. package figure 3. pin connection so-8 287 *1' *1' &203 9&& *1' *1' )% $09 www.st.com
contents AN1517 2/30 docid8827 rev 3 contents 1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 pwm comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 lc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 pwm comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.3 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid8827 rev 3 3/30 AN1517 contents 30 6 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 compensation network with mlcc (m ultiple layer ceram ic capacitor) at the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 external soft-start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
list of figures AN1517 4/30 docid8827 rev 3 list of figures figure 1. demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 3. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. internal regulator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. error amplifier equivalent circuit and compensati on network . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. short-circuit current v in = 25 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. short-circuit current v in = 30 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. pcb layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. pcb layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19. pcb layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. junction temperature vs. output current at v in = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. junction temperature vs. output current at v in = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22. efficiency vs. output current at v in = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 23. efficiency vs. output current at v in = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 24. positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25. buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 26. dual output voltage wi th auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 27. mlcc compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 28. soft-start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
docid8827 rev 3 5/30 AN1517 pin functions 30 1 pin functions pin description figure 4. block diagram table 1. pin description n. name description 1 out regulator output. 2gnd ground. lead connected directly to the frame in order to reduce the junction to ambient thermal resistance. 3gnd ground. lead connected directly to the frame in order to redu ce the junction to ambient thermal resistance. 4 comp e/a output to be used for frequency compensation. 5fb step-down feedback input. connecting the output voltage directly to this pin results in an output voltage of 1.235 v. an external re sistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7 k ? ). 6gnd ground. lead connected directly to the frame in order to reduce the junction to ambient thermal resistance. 7gnd ground. lead connected directly to the frame in order to reduce the junction to ambient thermal resistance. 8v cc unregulated dc input voltage. voltages monitor peak to peak current limit thermal shutdown e/a pwm 1.235v + - - + oscillator d ck q frequency shifter trimming supply 1.235v 3.5v driver v ref buffer lpdmos power fb gnd comp gnd gnd gnd out vcc am00028v1
functional description AN1517 6/30 docid8827 rev 3 2 functional description the main internal blocks are shown in the device block diagram in figure 4 . they are: ? a voltage regulator that supplies the internal circuitry. from this regulator, a 3.3 v reference voltage is externally available. ? a voltage monitor circuit which checks the input and internal voltages. ? a fully integrated sawtooth osc illator with a frequency of 250 khz 15%, including also the voltage feed-forward function and an input/output synchronization pin. ? two embedded current limitation circuits whic h control the current that flows through the power switch. the pulse-by-pulse curren t limit forces the po wer switch off cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle. ? a transconductance error amplifier. ? a pulse width modulation (pwm) comparator and the relative logi c circuitry necessary to drive the internal power. ? a high-side driver for t he internal p-mos switch. ? a circuit to implement the thermal protection function. 2.1 power supply an d voltage reference the internal regulator circuit (shown in figure 5 ) consists of a start-up circuit, an internal voltage ?preregulator?, the ?bandgap voltage reference? and the ?bias block? that provides current to all the blocks. the ?starter? gives the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). the ?preregulator block? supplies the ?bandgap cell? with a preregulated voltage v reg that has a very low supply voltage noise sensitivity. 2.2 voltages monitor an internal block continuously senses the v cc , v ref and v bg . if the voltages go higher than their thresholds, the regulator begins operat ing. there is also a hysteresis on the v cc (uvlo).
docid8827 rev 3 7/30 AN1517 functional description 30 figure 5. internal regulator circuit 2.3 oscillator figure 6 shows the block diagram of the oscillator circuit. the ?clock generator? provides the switching frequency of the device, which is internally fixed at 250 khz. the ?frequency shifter? block acts to reduce the switching frequency in case of strong overcurrent or short-circuit. the clock signal is then used in the internal logic circuitry and is the input of the ?ramp generator?. the ?ramp generator? circuit provides the sawtooth signal, used to for pwm control and the internal voltage feed-forward. figure 6. oscillator circuit block diagram 2.4 current protection the l5972d device has two types of current lim it protection: pulse-by-pulse and frequency foldback. the schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in figure 7 . the output power pdmos transistor is sp lit into two parallel pdmos transistors. the smallest one includes a resistor in series, r sense . the current is sensed through r sense and if it reaches the threshold, the mi rror becomes unbalanced and the pdmos is switched off until the next falling edge of the internal clock pulse. starter ic bias preregulator bandgap vreg vref am00006v1 v cc frequency shifter clock generator ramp generator synchronizator clock ramp ibias_osc sync t am00007v1 frequency shifter clock generator ramp generator synchronizer
functional description AN1517 8/30 docid8827 rev 3 due to this reduction of the on time, the output voltage decreases. since the minimum switch on time (necessary to avoid a false overcurrent signal) is too short to obtain a sufficiently low duty cycle at 250 khz, the output current, in strong overcurrent or short-circuit conditions, could increase again. for this reason the switching frequency is also reduced, thus keeping the inductor current under its maximum threshold. the frequency shifter ( figure 6 ) functions based on the feedback voltage. as the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also. figure 7. current limitation circuitry 2.5 error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose no n inverting input is connected to the internal voltage reference (1.235 v), while the inverting input (fb) is connected to the external divider or directly to the output voltage. the out put (comp) is connected to the external compensation network. the uncompensated error amplifier has the following characteristics: the error amplifier out put is compared with the oscillato r sawtooth to per form pwm control. 2.6 pwm comparator and power stage this block compares the oscillator sawtooth and the error amplif ier output signals generating the pwm signal for the driving stage. the power stage is a highly critical block, as it functions to guarantee a correct turn on and turn off of the pdmos. the turn on of the power element, or more accurately, the rise driver not a1 pwm vcc out a1/a2=95 i l rsense am00008v1 i off i i rth a2 table 2. uncompensated error amplifier characteristics description values transconductance 2300 s low frequency gain 65 db minimum sink/source voltage 1500 a/300 a output voltage swing 0.4 v/3.65 v input bias current 2.5 a
docid8827 rev 3 9/30 AN1517 functional description 30 time of the current at turn on, is a very critical parameter. at a first approach, it appears that the faster the rise time, the lo wer the turn on losses. however, there is a limit introduced by the recovery time of the recirculation diode. in fact, when the current of the power element is equal to the inductor current, the diode turns off and the drain of the power is able to go high. but during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for many problems: ? spikes on the device supply voltage that ca use oscillations (and thus noise) due to the board parasitics ? turn on overcurrent leads to a decrease in the efficiency and system reliability ? major emi problems ? shorter freewheeling diode life the fall time of the current during the turn off is also critical, as it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the pdmos. in order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in figure 8 . the basic idea is to change the current levels used to turn the power switch on and off, based on the pdmos and the gate clamp status. this circuitry allows the power switch to be turned off and on quickly and addresses the freewheeling diode recovery time problem. t he gate clamp is necessary to avoid that v gs of the internal switch goes higher than v gs max. the on/off control block protects against any cross conduction between the supply line and ground. figure 8. driving circuitry 2.7 thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 c). the sensing element of the chip is very close to the pdmos area, ensuring fast and accurate temperature detection. a hysteresis of approximat ely 20 c avoids that the device turns on and off continuously. vgs max gate stop drive drain off on pdmos vout drain vcc i load c esr am00009v1 i off i on on/off control clamp l
additional features and protection AN1517 10/30 docid8827 rev 3 3 additional features and protection 3.1 feedback disconnection if the feedback is disconnected, the duty cycl e increases towards the maximum allowed value, bringing the output voltage close to the input supply. this condition could destroy the load. to avoid this hazardous condition, the device is turned off if the feedback pin is left floating. 3.2 output overvoltage protection overvoltage protection, or ovp, is achieved by using an internal comparator connected to the feedback, which turns off the power stage when the ovp threshold is reached. this threshold is typically 30% higher than the feedback voltage. when a voltage divider is required to adjusting the output voltage ( figure 14 on page 21 ), the ovp intervention will be set at: equation 1 where r 1 is the resistor connected between the ou tput voltage and the feedback pin, while r 2 is between the feedback pin and ground. 3.3 zero load due to the fact that th e internal power is a pdmos, no bootstrap capacitor is required and so the device works properly even with no load at the output. in this condition it works in burst mode, with random burst repetition rate. v ovp 1.3 r 1 r 2 + r 2 --------------------- - ? v fb ? =
docid8827 rev 3 11/30 AN1517 closing the loop 30 4 closing the loop figure 9. block diagram of the loop 4.1 error amplifier an d compensation network the output l-c filter of a st ep-down converter contributes with 180 degrees phase shift in the control loop. for this reason a compensation network between the comp pin and ground is added. the simplest compensation net work together with the equivalent circuit of the error amplifier are shown in figure 10 . r c and c c introduce a pole and a zero in the open loop gain. cp does not sign ificantly affect system stability but it is useful to reduce the noise of the comp pin. the transfer function of the error amplifier and its compensation network is: equation 2 where a vo = g m r o a 0 s ?? a v0 1s + r c c c ? ? ?? ? s 2 r 0 ? c 0 c p + ?? r c c c sr 0 c c ? r 0 c 0 c p + ?? r c c c ? + ? + ?? 1 + ? + ? ? ? ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------- =
closing the loop AN1517 12/30 docid8827 rev 3 figure 10. error amplifier equivalent circuit and compensation network the poles of this transfer function are (if c c >> c 0 +c p ): equation 3 equation 4 where the zero is defined as: equation 5 f p1 is the low frequency which sets the bandwidth, while the zero f z1 is usually put near to the frequency of the double pole of the l-c filter (see section 4.2: lc filter ). f p2 is usually at a very high frequency. 4.2 lc filter the transfer function of the l-c filter is given by: equation 6 where r load is defined as the ratio between v out and i out . f p1 1 2 ? ? r 0 ? c c ? ------------------------------------- = f p2 1 2 ? ? r c ? c 0 c p + ?? ? ------------------------------------------------------- - = f z1 1 2 ? ? r c ? c c ? ------------------------------------- = a lc s ?? r load 1 esr c out s ? ? + ?? ? s 2 lc out esr r load + ?? s esr c out ? r load l + ? ?? r load + ? + ? ? ? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------- =
docid8827 rev 3 13/30 AN1517 closing the loop 30 if r load >> esr, the previous expression of a lc can be simplified and becomes: equation 7 the zero of this transfer function is given by: equation 8 f 0 is the zero introduced by the esr of the ou tput capacitor and it is very important to increase the phase margin of the loop. the poles of the transfer function can be calculated through the following expression: equation 9 in the denominator of a lc, the typical second order system equation can be recognized: equation 10 if the damping coefficient ? is very close to zero, the roots of the equation become a double root whose value is ? n . similarly, for a lc the poles can usually be defined as a double pole whose value is: equation 11 4.3 pwm comparator the pwm gain is given by the following formula: equation 12 where v oscmax is the maximum value of a sawtooth waveform and v oscmin is the minimum value. a voltage feed-forward is implemented to ensure a constant gpwm. this is obtained by generating a sawtooth waveform directly proportional to the input voltage v cc . a lc s ?? 1 esr c out ? s ? + lc out ? s 2 esr c out ? s1 + ? + ? ---------------------------------------------------------------------------------------------- = f o 1 2 ? ? esr ? c out ? --------------------------------------------------- - = f plc1 2 ? esr c out esr c out ? ?? 2 4l ? c out ? ? ? ? ? 2l ? c out ? ------------------------------------------------------------------------------------------------------------------------------- ----------- = s 2 2 ? ?? n ? s ? 2 n + ? + f plc 1 2 ? ? lc out ? ? ---------------------------------------------- = g pwm s ?? v cc v oscmax v oscmin ? ?? ------------------------------------------------------------- =
closing the loop AN1517 14/30 docid8827 rev 3 equation 13 where k is equal to 0.076. therefore the pwm gain is also equal to: equation 14 this means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and line transient response. to sum up, the open loop gain can be written as: equation 15 example 1 ? considering r c = 2.7 k ? , c c = 22 nf and c p = 220 pf, the poles and zeroes of a 0 are: ? f p1 = 9 hz ? f p2 = 256 khz ? f z1 = 2.68 khz ? if l = 22 h, c out = 100 f and esr = 80 m ? , the poles and zeroes of a lc become: ? f plc = 3.39 khz ? f 0 = 19.89 khz finally r 1 = 5.6 k ? and r 2 = 3.3 k ? . the gain and phase bode diagrams are plotted respectively in figure 11 and figure 12 . figure 11. module plot v oscmax v oscmin ? kv cc ? = g pwm s ?? 1 k --- - const == gs ?? g pwm s ?? r 2 r 1 r 2 + -------------------- ? a o s ?? ? a lc ? s ?? =
docid8827 rev 3 15/30 AN1517 closing the loop 30 figure 12. phase plot the cut off frequency and the phase margin are: equation 16 f c = 22.8 khz phase margin = 39.8
application information AN1517 16/30 docid8827 rev 3 5 application information 5.1 component selection 5.1.1 input capacitor the input capacitor must be able to withstand the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the input capacitor has to absorb all this switching curr ent, which can be up to the load current divided by two (worst case, with duty cycle of 50%). for this reason, the quality of these capacitors has to be very high to minimize its power dissipation genera ted by the internal esr, thereby improving system reliability and efficiency. the critical parameter is usually the rms current rating, which must be higher than the rms input current. the maximum rms input current (flowing through the input capacitor) is: equation 17 where ? is the expected system efficiency, d is the duty cycle and i o the output dc current. this function reaches its maximum value at d = 0.5 and the equivalent rms current is equal to i o divided by 2 (considering ? = 1). the maximum and minimum duty cycles are: equation 18 where v f is the freewheeling diode forward voltage and v sw the voltage drop across the internal pdmos. considering the range d min to d max , it is possible to determine the max i rms going through the input capacitor. capacitors that can be considered are: ? electrolytic capacitors: these are widely used due to their low price and their availability in a wide range of rms curr ent ratings. the only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. ? ceramic capacitors: if available for the required value and voltage rating, these capacitors usually have a higher rms current rating for a given physical dimension (due to very low esr). the drawback is the considerably high cost. ? tantalum capacitor: good, small tantalum capacitors with very low esr are becoming more available. however, they can occasiona lly burn if subjected to very high current during charge. therefore, it is better to avoid this type of capacitor for the input filter of the device. they can, however, be subjected to high surge current when connected to the power supply. i rms i o d 2d 2 ? ? ----------------- - ? d 2 ? ------- + ? = d max v out v f + v inmin v sw ? ------------------------------------------ = d min v out v f + v inmax v sw ? -------------------------------------------- = and
docid8827 rev 3 17/30 AN1517 application information 30 5.1.2 output capacitor the output capacitor is very important to me et the output voltage ripple requirement. using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. so, to reduce the output voltage ripple, a low esr capacitor is required. nevertheless, the esr of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. if the zero goes to a very high frequency, its effect is negligible. for this reason, ceramic capacitors and very low esr capacito rs in general should be avoided. tantalum and electrolytic capacitors are usually good for this purpose. table 3 below provides a list of some tantalum capacitor manufacturers. 5.1.3 inductor the inductor value is very important because it fixes the ripple cu rrent flowing through output capacitor. the ripple current is usually fixed at 20-40% of i o max, which is: 0.3 - 0.6 a with i o max = 1.5 a. the approximate inductor value is obtained using equation 19 : equation 19 where t on is the on time of the internal switch, given by d t. for example, with v out = 3.3 v, v in = 12 v and ? i o = 0.45 a, the inductor value is about 21 h. the peak current through the inductor is given by: equation 20 and it can be observed that if the inductor va lue decreases, the peak current (which must be lower than the current limit of the device) in creases. so, when the peak current is fixed, a higher inductor value allows a higher value for the output current. table 3. recommended output capacitors manufacturer series cap value ( ? f) rated voltage (v) esr (m ? ) avx tps 100 to 470 4 to 35 50 to 200 kemet t494/5 100 to 470 4 to 20 30 to 200 sanyo poscap (1) 1. poscap capacitors have characterist ic very similar to tantalum ones. tpa/b/c 100 to 470 4 to 16 40 to 80 sprague 595d 220 to 390 4 to 20 160 to 650 l v in v out ? ?? i ? -------------------------------------- - t on ? = i pk i o i ? 2 ---- - + =
application information AN1517 18/30 docid8827 rev 3 in table 4 , some inductor manufacturers are listed. 5.2 layout considerations the layout of switching dc-dc converters is very important to minimize noise and interference. power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. high impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as po ssible from the high current paths. a layout example is provided in figure 13 . the input and output loops are minimized to avoid radiation and high frequency resonance problems. the feedback pin connections to the ex ternal divider are very close to the device to avoid pick-up noise. moreover, the gnd pi n of the device is connected to the ground plane directly with via on the bottom side of the pcb. figure 13. layout example table 4. inductor selection manufacturer series inductor value ( h) saturation current (a) coilcraft do3316 33 to 47 1.6 to 2 coiltronics up2b 33 to 47 1.7 to 2 bi hm76-3 33 to 47 2 to 2.5 epcos b82476 33 to 47 1.6 to 2 wurth elektronik 744561 33 to 47 1.6 to 2 l5972d cin d cout l to output voltage vin vout gnd r1 r2 1 4 5 8 very small high current circulating path to minimize radiation and high frequency resonance problems output capacitor directly connected to heavy ground compensation network far from high current paths minimun size of feedback pin connections to avoid pickup connection to groundplane through vias am00131v1 l5972d
docid8827 rev 3 19/30 AN1517 application information 30 5.3 thermal considerations the dissipated power of the device is tie to three different sources: ? switch losses due to the not negligible r dson . these are equal to: equation 21 where d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between v out and v in , but in practice it is substant ially higher than this value to compensate for the losses of the overall applic ation. for this reason, the switching losses related to the r dson increase compared to an ideal case. ? switching losses due to turning on and off. these are derived using equation 22 : equation 22 where t on and t off are the overlap times of the voltage across the power switch and the current flowing into it during the turn on and turn off phases. t sw is the equivalent switching time. ? quiescent current losses. equation 23 where i q is the quiescent current. example 2 ?v in = 5 v ?v out = 3.3 v ?i out = 1.5 a r dson has a typical value of 0.25 ? at 25 c and increases up to a maximum value of 0.5 ? at 150 c. we can consider a value of 0.4 ? . t sw is approximately 70 ns. i q has a typical value of 2.5 ma at v in = 12 v. the overall losses are: equation 24 the junction temperature of device will be: equation 25 where t a is the ambient temperature and rth j-a is the thermal resistance junction to ambient. p on r dson i out ?? 2 ? d ? = p sw v in i out ? t on t off + ?? 2 ---------------------------------------- - ? f sw ? v in i out ? t sw ? f sw ? == p q v in i q ? = p tot r dson i out ?? 2 dv in i out t sw f sw v in i q = ? + ??? + ?? = 0.4 1.5 2 0.7 51.57010 9 ? 250 10 3 52.510 3 ? 0.9w ? ?? + ??? ? ? + ?? =
application information AN1517 20/30 docid8827 rev 3 considering that the device in so-8 (4+2+2) package mounted on board with a good groundplane has a thermal resistance junction to ambient (rth j-a ) of about 62 c/w and considering an ambient temperature of about 70 c. equation 26 5.4 short-circuit protection in overcurrent protection mode, when the peak current reaches the current limit, the device reduces the t on down to its minimum value (approximately 250 ns) and the switching frequency to approximately one third of its nominal value (see section 2.4: current protection on page 7 ). in these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to i lim . in any event, in case of heavy short- circuit at the output (v out = 0 v) and depending on the application conditions (v cc value and parasitic effect of external components), the current peak could reach values higher than i lim . this can be understood considering the inductor current ripple during the on and off phases: ? on phase equation 27 ? off phase equation 28 where v d is the voltage drop across the diode, and dcr l is the series resistance of the inductor. in short-circuit conditions v out is negligible. so, during the t off , the voltage applied to the inductor is very small and it may be that the current ripple in this phase does not compensate for the current ripple during the t on . the maximum current peak can be easily measured through the inductor with v out = 0 v (short-circuit) and v cc = v in max. in cases where the applic ation must sustain the short- circuit condition for an extend ed period, the external components (mainly the inductor and diode) must be selected based on this value. t j 70 0.9 62 128 ? c ? ? + = i l ? v in v out dcr l i ? ? ? ?? l -------------------------------------------------------------------- - t on ? = i l ? v d v out dcr l i ? ++ ?? l ------------------------------------------------------------------ t off ? =
docid8827 rev 3 21/30 AN1517 application information 30 figure 14. short-circuit current v in = 25 v figure 15. short-circuit current v in = 30 v in figure 14 and figure 15 , for example, it can be observed that when the input voltage increases for a given component list, the current peak increases also. the current limit is immediately triggered but the current peak increases until the current ripple during the t off is equal to the current ripple during the t on . 5.5 application circuit figure 16 shows the demonstration board applicat ion circuit for the device in the smd version, where the input supply voltage, v cc , can range from 4.4 v to 25 v due to the rated voltage of the input capacitor and the output voltage is adjustable from 1.235 v to v cc . figure 16. demonstration board application circuit i l vout i limit i l vout i limit 8 2 4 5 1 7 l5972d c1 10 f 25v ceramic c2 100 f 10v vout=3.3v vin = 4.4v to 25v r1 5.6k r2 3.3k r3 4.7k c4 22nf c3 220pf 3 l1 33 h 6 d1 stps2l25u comp vcc out fb gnd am00027v1 l5972d
application information AN1517 22/30 docid8827 rev 3 table 5. component list reference part number de scription manufacturer c1 10 f, 25 v tokin c2 poscap 10tpb100m 100 f, 10 v sanyo c3 c1206c221j5gac 220 pf, 5%, 50 v kemet ? c4 c1206c223k5rac 22 nf, 10%, 50 v kemet r1 5.6 k ? , 1%, 0.1 w 0603 neohm ? r2 3.3 k ? , 1%, 0.1 w 0603 neohm r3 4.7 k ? , 1%, 0.1 w 0603 neohm d1 stps2l25u 2 a, 25 v stmicroelectronics ? l1 do3316p-333 33 h, 2.1 a coilcraft
docid8827 rev 3 23/30 AN1517 application information 30 figure 17. pcb layout (component side) figure 18. pcb layout (bottom side) figure 19. pcb layout (front side)
application information AN1517 24/30 docid8827 rev 3 in figure 20 to figure 23 are some graphs showing the t j versus output current in different input and output voltage conditions. figure 20. junction temperature vs. output current at v in = 5 v figure 21. junction temperature vs. output current at v in = 12 v 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 io(a) tj(c) vin=5v tamb.=25 c vo=1.8v vo=2.5v vo=3.3v 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 io(a) tj(c) vo=2.5v vo=3.3v vo=5v vin=12v tamb= 25c figure 22. efficiency vs. output current at v in = 5 v figure 23. efficiency vs. output current at v in = 12 v 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 io (a) efficiency (%) vo=1.8v vo=2.5v vo=3.3v vin=5v vo=1.8v vo=2.5v vo=3.3v 70 72 74 76 78 80 82 84 86 88 90 92 94 96 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 io (a) efficiency (%) vin=12v vo=2.5v vo=3.3v vo=5v vin=12v vo=2.5v vo=3.3v vo=5v
docid8827 rev 3 25/30 AN1517 application ideas 30 6 application ideas positive buck-boost regulator the device can be used to implement an st ep-up/down converter with a positive output voltage. figure 24 shows the schematic diagram of this topology for an output voltage of 12 v. the input voltage can range from 5 v and 35 v. the output voltage is given by v o = v in d / (1 - d), where d is the duty cycle. the maximum output current is given by i out = 1 (1 - d). the current cap ability is reduced by the term (1 - d) and so, for example, with a duty cycle of 0.5, the maximum output curren t deliverable to the load is 0.75 a. this is due to the fact that the current flowing through the internal power switch is delivered to the output only during the off phase. figure 24. positive buck-boost regulator 7 buck-boost regulator in figure 25 , the schematic circuit for a standard buck -boost topology is shown. the output voltage is given by v o = -v in d / (1 - d). the maximum output current is equal to i out = 1 (1 - d), for the same reason as that of the up-down converter. an important thing to take in account is that the ground pin of th e device is connected to the negative output voltage. therefore, the device is subjected to a voltage equal to v in - v o , which has to be lower than 36 v (the maximum operating input voltage). figure 25. buck-boost regulator vin=5v c1 10uf 10v ceramic d1 stps2l25u vcc comp gnd out fb l5972d 1 3 7 5 6 4 8 2 r3 4.7k l1 33uh 24k 2.7k c3 22nf c4 100uf 16v vout=12v/0.45a c2 220pf d2 stps2l25u m1 stn4ne03l am00136v1 l5972d vin=5v c1 10uf 10v ceramic d1 stps2l25u vcc comp gnd out fb l5972d 1 3 7 5 6 4 8 2 r3 4.7k l1 33uh 2.7k 24k c4 22nf c5 100uf 16v vout=-12v/0.45a c3 220pf c2 10uf 25v ceramic am00135v1 l5972d
buck-boost regulator AN1517 26/30 docid8827 rev 3 dual output voltage wi th auxiliary winding when two output voltages are required, it is possible to create a dual output voltage converter by using a coupled inductor. during the on phase the current is delivered to v out while d2 is reverse-biased. during the off phase, the curr ent is delivered through the au xiliary winding to the output voltage v out1 . this is possible only if the magnetic core has stored sufficient energy. so, to be certain that the application is working pro perly, the load related to the second output v out1 should be much lower than the load related to v out . figure 26. dual output voltage with auxiliary winding vin=12v c1 10uf 25v d1 stps2l25u vcc comp gnd out fb l5972d 1 3 7 5 6 4 8 2 r3 4.7k c3 22nf c4 100uf 10v vout=3.3v c2 220pf vout1=5v 50ma d2 stps2l25u c5 47uf 10v n1 n2 n=n1/n2=2 am00137v1 l5972d
docid8827 rev 3 27/30 AN1517 compensation network with mlcc (multi ple layer ceramic capacitor) at the output 30 8 compensation network with mlcc (multiple layer ceramic capacitor) at the output mlccs with values in the range of 10 f - 22 f and rated voltages in the range of 10 v - 25 v are available today at relatively low cost from many manufacturers. these capacitors have very low esr values (a few m ? ) and thus are occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application. however, a very low esr value affect s the compensation of the loop (see section 4: closing the loop on page 11 ) and in order to keep the system stable, a more complicated compensation network may be required. figure 27 shows an example of compensation network that stabilizes the s ystem with ceramic ca pacitors at the ou tput (the optimum component value depends on the application). figure 27. mlcc compensation network example external soft-start network at the startup, the device can quickly increase th e current up to the curr ent limit in order to charge the output capacitor. if a soft ramp-up of the output voltage is required, an external soft-start network can be implemented as shown in figure 28 . the capacitor c is charged up to an external reference (through r), and the b jt clamps the comp pin. this clamps the duty cycle, limiting the slew rate of the output voltage. 4.7uh l1 vin=5v c1 mlcc 10uf d1 vcc comp gnd out fb 1 3 7 5 6 4 8 2 r3=2.2k coilcraft c4=4.7nf c2 mlcc 22uf 6.3v l5972d vout=2.1v c5=2.7nf r4=470 r1=3.3k c3=220pf r2=4k7 stps2l25u 4.7uh l1 vin=5v c1 mlcc 10uf d1 vcc comp gnd out fb 1 3 7 5 6 4 8 2 r3=2.2k coilcraft c4=4.7nf c2 mlcc 22uf 6.3v l5972d vout=2.1v c5=2.7nf r4=470 r1=3.3k c3=220pf r2=4k7 stps2l25u am00138v1 l5972d
compensation network with mlcc (multiple layer ceramic capacitor) at the output AN1517 28/30 docid8827 rev 3 figure 28. soft-start network example l1 vin=4.4v to 25v c1 10uf 25v ceramic d1 stps2l25u vcc comp gnd out fb 1 3 7 5 6 4 8 2 r3=4.7k 33uh coilcraft c4=22nf c2 100uf 10v l5972d vout=3.3v c3=220pf vref r=4k7 css=2.7nf bc327 r1=5.6k r2=3.3k l1 vin=4.4v to 25v c1 10uf 25v ceramic d1 stps2l25u vcc comp gnd out fb 1 3 7 5 6 4 8 2 r3=4.7k 33uh coilcraft c4=22nf c2 100uf 10v l5972d vout=3.3v c3=220pf vref r=4k7 vref r=4k7 css=2.7nf bc327 r1=5.6k r2=3.3k am00139v1 l5972d
docid8827 rev 3 29/30 AN1517 revision history 30 9 revision history table 6. document revision history date revision changes 08-nov-2006 1 first issue 28-may-2007 2 ? the document has been reformatted ? section 4: closing the loop modified ? minor text changes 13-nov-2013 3 ? updated title and figure 1 on page 1 (replaced l5970 by steval- isa089v1). ? updated figure 17 , figure 18 and figure 19 on page 23 (replaced l5970 by l5972d device). ? updated figure 3 (replaced sync, inh, a nd vref pins by gnd, minor corrections). ? updated section 2.4 (replaced l5973ad device by l5972d device). ? updated titles of figure 20 to figure 23 (added v in = 5/12 v, in figure 22 replaced junction temperature by efficiency). ? minor modifications throughout document.
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